Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

rickman wrote:
On Jul 6, 10:51 am, "Ulf Samuelsson" <u...@xxxxxxxxxxxxx> wrote:

The FIFO is implemented using Flip-Flops and you had a
simple three stage pipeline (fetch, decode,execute) so
your latency was not dramatic.


That is not the point. By prefetching the instructions, you are
setting up for a bigger dump and subsequent loss of instruction memory
bandwidth when you branch. FIFOs or instruction prefetching are not a
perfect solution. It is much better to just have single cycle
memory.



If you have one waitstate, you will see that the bandwidth is still high

Yes, but if the jumps are probably only 10-20% of all instructions
so you lose only between 10-20% of the performance instead of 50%.
The AVR32 loses less than 10% in average.


But you are comparing apples and oranges. A processor that has no
wait states doesn't have to deal with this no matter what the
instruction mix is. It is just much simpler to not have to consider
memory latencies.

Of course, yes it "is much better to just have single cycle
memory" - but in the real world, chip designers have to settle on
what they can get, and right now, FLASH access speeds are a real
bottleneck on uC performance.

Width of FLASH access, (or Interleave), can have MORE impact on final
speed, than any subtleness in the core itself.



I have run the SAM7 at 48 MHz, zero waitstate. Does not work over the
full
temp range though.
The AVR32 will support 1.2 MIPS/MHz @ 1 waitstate operation @ 66 MHz
due to its 33 MHz 2 way interleaved flash memory.
(1st access after jump is two clocks, subsucquent accesses are 1 clock)

How does that compare to the Cortex M3 running at 50 MHz with no
waitstates and no branch penalty?

The UC3000 is claimed as 80 MIPS at 66 MHz.
For the Cortex M3 to reach 80 MIPS at 50 MHz,
you have to have 80/50 = 1,6 MIPS per MHz.
I think that ARM does not claim that the Cortex is close to 1,6 MIPS per
MHz.


Oh, this is marketing stuff. I thought you might have run some real
benchmarks or someone else at Atmel might have. Certainly they have
looked hard at the Cortex. But if it competes too well against the
AVR32, I can see why it would not be pushed at Atmel. Certainly there
will be a lot of sockets that will be won by an ARM device over a sole
source part like the AVR32. At this point I don't think anyone can
say whether the AVR32 has legs and will be around in 5 years. It has
been out for what, a year or so?

You can say (almost) the same for the CortexM3 ?
It too is quite new, and I've not seen any multi-sourced (pin/peripheral compatible) offerings. Will it hit 'critical mass' ?
From a porting viewpoint, an Atmel ARM7 user, could find it less of
a jump to go to AVR32 (or the comming Atmel Flash ARM9's), than CortexM3, as the Atmel peripherals are very similar.

The AVR32 I see as having a long life, it seems to have low cost tool
flows, and good debug support. (Don't underestimate the importance of
good debug support.)

The actual uC Cores matter less and less : package and peripherals have
determined our shortlists in latest projects - and the ST Cortex even made it onto the list, on that basis, until we found their serious oops, that CAN and USB were mutually exclusive ?!?

Then, there is the new Coldfire V1 core from Freescale. Choices, Choices....

-jg

.

Relevant Pages

  • Re: AVR32 availablilty ?
    ... Whether a core has a divide or a MAC ... instruction is not as relevant as the ability to run real world code ... Just do a series of MACs where you check for saturation and the AVR32 ... There is a difference between DSP "operations" and DSP ...
    (comp.arch.embedded)
  • Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics
    ... setting up for a bigger dump and subsequent loss of instruction memory ... For the Cortex M3 to reach 80 MIPS at 50 MHz, ... AVR32, I can see why it would not be pushed at Atmel. ... Reading internal SRAM is a one clock cycle operation on the AVR32. ...
    (comp.arch.embedded)
  • Re: AVR32 availablilty ?
    ... Whether a core has a divide or a MAC ... instruction is not as relevant as the ability to run real world code ... You're as usual spinning marketing lies. ... Just do a series of MACs where you check for saturation and the AVR32 will ...
    (comp.arch.embedded)