Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

Ulf Samuelsson wrote:
"rickman" <gnuarm@xxxxxxxxx> skrev i meddelandet
That is not the point. By prefetching the instructions, you are
setting up for a bigger dump and subsequent loss of instruction memory
bandwidth when you branch. FIFOs or instruction prefetching are not a
perfect solution. It is much better to just have single cycle
memory.

Actually it is not, because if you try to decode your instruction
in the same stage as the decoding, your clock frequency will
go down significantly.
The prefetching will work with single cycle memory and with
memory having waitstates.

What are you talking about??? How is slow memory faster than fast
memory???


Prefetching, decoding and execution, all will take one clock.
If you execute at 66 MHz with a three stage pipeline
then you probably will execute around ~40 MHz with
a two stage pipeline (Just a guess).

If you execute blocks of 5 instruction including one jump,
each block will use 7 cycles (3 + 1 + 1 + 1 + 1) @ 66 Mhz
in a three stage pipeline for ~ 10 blocks / us.

In a two stage pipeline, you could use 2 clocks for a jump
so you execute (2 + 1 + 1 + 1 + 1) @ 40 MHz
which is 6,5 blocks / us, clearly slower.

Since when do I get to design my own processor??? Everything you have
just written is based on your own assumptions. This is a pointless
discussion since everything you say is based on *your* assumptions!
In addition, you only consider the parts of the issue that you choose
to include. You did a timing analysis on paper that does not include
the effect of branches. Clearly not accurate regardless of your
assumptions!



But you are comparing apples and oranges. A processor that has no
wait states doesn't have to deal with this no matter what the
instruction mix is. It is just much simpler to not have to consider
memory latencies.


A processor running from flash without wait states will be limited
in performance by the memory.
A processor which reads multiple instructions with wait state
will be able to execute faster due to its higher bandwidth to memory.

Again you are assuming facts that are not in evidence. Where do you
get the higher bandwidth from memory if it is running with wait
states? Oh, right, you are *assuming* that there is something
different in the design that will make that one faster. Something
that is not part of a slower Flash that requires wait states.


The UC3000 is claimed as 80 MIPS at 66 MHz.
For the Cortex M3 to reach 80 MIPS at 50 MHz,
you have to have 80/50 = 1,6 MIPS per MHz.
I think that ARM does not claim that the Cortex is close to 1,6 MIPS per
MHz.

Oh, this is marketing stuff. I thought you might have run some real
benchmarks or someone else at Atmel might have.

They have run benchmarks on the AVR32, but I think people are relying
on official figures for the Cortex.

"People" being "you"?


Certainly they have
looked hard at the Cortex. But if it competes too well against the
AVR32, I can see why it would not be pushed at Atmel.
Certainly there
will be a lot of sockets that will be won by an ARM device over a sole
source part like the AVR32.

And hopefully ARM device from Atmel :-)

There are a number of sockets that Atmel won't win if they don't have
a CM3 device. There are two companies with the new core in production
and a third on their heels. I am sure sales of the ARM7 devices won't
drop off a cliff. But this business is all about design wins and I
stand by my earlier post in another thread that the CM3 will start to
steal significant numbers of design wins by the end of this year and
by the end of next year they will overshadow the ARM7 design wins in
the off the shelf MCU market.


At this point I don't think anyone can
say whether the AVR32 has legs and will be around in 5 years. It has
been out for what, a year or so?


Fortunately there are plenty of sockets around, and some will go AVR32.

Is that the plan for the AVR32, to take *some* sockets? You know as
well as I do that if the AVR32 does not get significant market
penetration within a two years from now, it will be put on the back
burner and eventually discontinued. Atmel has no reason to keep making
a part that consumes significant resources and does not make
significant profit. Look at what happened to Atmel programmable
logic. When was the last time they added a new FPGA to the product
line? How many FPSLICs have been designed into new sockets?


The AVR32 is decidedly better on DSP algorithms due to its
single cycle MAC and also it has faster access to SRAM.
Reading internal SRAM is a one clock cycle operation on the AVR32.
Bit banging will be one of the strengths of the UC3000.

Isn't reading internal SRAM a single cycle on *all* processors? I
can't think of any that require wait states. In fact, most processors
try to cram as much SRAM onto the chip as possible because it is so
fast. Did you say what you meant to say?


On the UC3000 family, loading from internal SRAM will take one clock
in the execution stage.
Using single cycle SRAM does not mean that the load instruction is 1 clock.

Like I said, aren't all internal SRAMs in all processors single
cycle???

.

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