Re: Pipeline induced interrupt latency jitter


"Didi" <dp@xxxxxxxxxxx> wrote in message
news:1184888984.497011.17440@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
I wonder if the new SHARC DSPs which I recall reading are not pipelined,
could produce perfectly jitter-free signal synthesis?

Not pipelined does not mean one cycle per any opcode. Only if the
Blackfin does that (I don't know, I have only looked at it and not
used it) can zero latency jitter be expected.

This is not right.

Blackfin has a pipeline of 8 clock cycles deep, plus 32 bytes of prefetch,
DMAs, code/data caches and multiple buses with complex arbitration. Due to
that, the interrupt latency can be wildly different. Actually it is so
different that it is difficult to account for the worst case.

If it has division,
there we
go, I have yet to see a single cycle div :-). But then again, if they
do the div in the TI style (in a loop using "conditional subtract" or
whatever it was, it's been years since I last did that), this can be
interruptable.... Yet 0 IRQ latency jitter would be quite a feature,
I guess I would have noticed _that_ when I was looking
at the Blackfin.

The main idea of BlackFin is that the interrupts should not be used for the
critical jitter free timing. There is a number of built in peripherals
(PPIs, SPORTs, DMAs) which generate the timings by hardware.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com



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Relevant Pages

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