Re: New ARM Cortex Microcontroller Product Family from STMicroelectronics

rickman wrote:

Nope it isn't, the AVR32 running at 66 MHz will run mostly
at zero waitstates due to its interleaved flash controller design.
Each flash access done by the memory controller
will have 1 waitstate, but since the memory controller can do
two accesses in parallel, the CPU will only see waitstates
during jumps, and no waitstates during non jump instructions.
If you do jumps 20% of the time, then the average number of waitstates is
0,2.
On top of that you will be able to perform dataaccesses to the flash
while eating from the instruction queue wihout any performance penalty.


That is pointless. It does not matter how large the FIFO is, if you
are pulling data out at a given rate and you can only put data in at
that same rate, as soon as you have to stop instruction reads to do a
data read, you will not be filling the FIFO as fast as it is being
emptied and performance will suffer. Run through a simulation and see
if that is not true. Based on the info you provided, this is the
result.



On Cortex-M3 (and possibly AVR32 ? ), many instructions are 16-bit.
As a result, the instruction bus (32-bit) fetch upto two instructions each cycle, while most of the time only one instructions is executed per cycle. So it is possible to stall the instruction fetch for a cycle to to fetch data from flash, without seeing any stall at the execution stage.

Joseph
.

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