Re: 66MIPS 8bit microcontroller

On Jul 27, 12:47 pm, moja...@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx (Everett M.
Greene) wrote:
"Wilco Dijkstra" <Wilco_dot_Dijks...@xxxxxxxxxxxx> writes:
"Steve at fivetrees" <st...@xxxxxxxxxxxxxxxxxxxxx> wrote
"Anton Erasmus" <nob...@xxxxxxxxxxxxxxxx> wrote

http://www.tezzaron.com/OtherICs/Super_8051.htm

I see that they say that their 200MHz almost 1 cycle per instruction
with hardware IEEE floating point support runs almost 3x faster than
a standard 8051 computing a mandelbrot pattern. Am I missing
something, or is this just slightly short of pathetic ? Just based on
the clock frequency and less clock cycles per machine cycle, their
8051 should be close to 150x faster.

Given that they also say "up to 100 MFlops", I suspect they're comparing with/without the hardware IEEE on the same
"standard" 8051 at the same clock speed. Although even then, I think I'd expect slightly better...

A quick look at the data*** shows that a floating point operation takes
8 moves to set up the input operands, 1 to set the operation and 4 to store
the result (which is valid after 4 cycles). So that's 8 * 4 + 3 + 4 * 4 + 4 = 55
cycles for one floating point operation. This gives 3.6MFlops at 200MHz, a
little lower than the claimed 100MFlops. Similarly the 200MIPS maximum
speed is more like 75MIPS on actual code as few instructions execute in
1 cycle.

A software floating point implementation on this 8-bit core might take around
200 cycles on average for addition/multiply, so getting a factor 3 speedup
from the floating point hardware sounds feasible. Not very impressive indeed.

I think you'll find that float operations on an 8-bit micro are
going to require much more than 200 cycles. Addition will be of
the order of 1000 cycles and multiply/divide/sqrt nearer 3000.- Hide quoted text -

- Show quoted text -


200 cycles is about right for add, substract and multiply, see Keil's
Complier peformance benchmarks for the 8051

http://www.keil.com/benchmarks/c51_tm_small.asp



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