Re: Synchronized SPI communication

On Sep 28, 3:05 pm, larwe <zwsdot...@xxxxxxxxx> wrote:
On Sep 28, 7:43 am, Vivek B <vivekb1...@xxxxxxxxx> wrote:

I am trying to implement interrupt based SPI communication between two
Atmel microcontrollers. The data has to be transmitted from slave to
master.

I didn't look at your problem in detail, but before you go any further
try your code with a different data pattern than 0xFF. Choose say 0x10
or 0x08. FF is a bad test case because you can't see if you are
missing bits in between bytes.

His problem is probably on a per byte basis, not per bit.

I had this - well, as long ago as 1994 was... - when I defined an SPI
channel per Nukebus slot (which is a 16-data/8 address bits interface)
to have some means to deal with the many infrequently changing bits
a device typically has over less wires.
Since SPI is host driven the host must poll the slave, and must send
new data no faster than the slave can process (or buffer) it.
Then the host has no way of knowing whether upon sending a byte
what it gets over the same 8 clocks is the byte it has sent
in the previous 8 clocks or data which the slave has written to the
output register in the meantime.
So I defined the protolol as a 7 bit (7 bits per byte, that is).
Any data the host sends has bit 7 set 0, and any data the slave sends
has bit 7 set to 1; the host uses bit 7 in its input stream to
determine
whether the slave has output a byte. The host sends a 0
to poll the slave which the slave has to ignore.
This has worked ever since. The slave processing speed
is defining, it often can be not so fast a protocol as SPI is
for driving, say, a DAC or something; the host has to wait between
bytes it sends to prevent the slave from missing a byte due to
receiver
overrun.

Dimiter

------------------------------------------------------
Dimiter Popoff Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

.

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