Re: Transmitting over SSC using PDC at AT91SAM9261

FreeRTOS.org wrote:
"Andreas Kuehn" <kuehn@xxxxxx> wrote in message news:fdsqgd$lc0$1@xxxxxxxxxxx
Hello out there...

I'm trying to send a block of data using the Peripheral DMA Controller (PDC) over the SSC-0. As transmitter and receiver of the SSC are independent and the PDC is full duplex capable, sending and receiving at the same time should be possible.
But I can't get the PDC transfer going! Word by word transmissions work fine and the TK and TF signals are fine too. Nevertheless, if I activate the PDC I don't see any data running over the TD line.

Can you give me a hint on what is usually the "fault"? Or even an example for the AT91SAM92xx controller?

Thanks in advance
akuehn

I have the SSC running with the PDC but am not able to share the code (it was developed specifically for a customer). If you post your initialisation function I might be able to suggest something though.



Here what I did so far. I mean register configuration of the SSC0 to perform a continuous data transfer of 16 long words per PDC call.

/**
* Serial Synchronous Controller (SSC) definitions concerning
* speed and protocoll.
*
*/
#define SSC_WORD_SIZE 32 // Bit
#define SSC_NUMBER_OF_WORDS 16 // WORDS
#define SSC_PERIOD 0xff // (Bit x Words)/2 -1
#define SSC_FSLEN (1 -1) // length of frame sync bit
#define SSC_DATNB (16 -1) // DATANB +1
#define SSC_DATLEN (32 -1) // Word length


#define RCMR_VAL ((SSC_PERIOD << 24) \
| AT91C_SSC_STOP \
| AT91C_SSC_START_FALL_RF \
| AT91C_SSC_CKG_NONE \
| AT91C_SSC_CKI \
| AT91C_SSC_CKO_CONTINOUS \
| AT91C_SSC_CKS_RK)

#define RFMR_VAL (AT91C_SSC_FSEDGE \
| AT91C_SSC_FSOS_POSITIVE \
| (SSC_FSLEN << 16) \
| (SSC_DATNB << 8) \
| AT91C_SSC_MSBF \
| (SSC_DATLEN << 0))

#define TCMR_VAL ((SSC_PERIOD << 24) \
| AT91C_SSC_START_FALL_RF \
| AT91C_SSC_CKG_NONE \
| AT91C_SSC_CKI \
| AT91C_SSC_CKO_CONTINOUS \
| AT91C_SSC_CKS_DIV)

#define TFMR_VAL (AT91C_SSC_FSEDGE \
| AT91C_SSC_FSDEN \
| AT91C_SSC_FSOS_POSITIVE \
| (SSC_FSLEN << 16) \
| (SSC_DATNB << 8) \
| AT91C_SSC_MSBF \
| (SSC_DATLEN << 0))



And here we have the initialization function, the way I thought it is correct (?).

AT91PS_SSC initSSC_0(void)
{
AT91PS_SSC pSSC = AT91C_BASE_SSC0;
AT91PS_AIC pAIC = AT91C_BASE_AIC;
volatile unsigned int status;


/* Configure PIOB pins to drive SSC0 signals */
AT91F_SSC0_CfgPIO ();

/* Enable the peripheral clock at the PMC */
AT91F_SSC0_CfgPMC ();

/* SSC configuration for sender and receiver */
AT91F_SSC_Configure (pSSC, AT91B_MCK, AT91B_MCK/4000,
RCMR_VAL, RFMR_VAL, TCMR_VAL, TFMR_VAL);

// Enable Transmit
AT91F_SSC_EnableTx (pSSC);

// Enable Receive
AT91F_SSC_EnableRx (pSSC);


// Disable all interrupts
AT91F_SSC_DisableIt (pSSC, 0xffffffff);

/* Clear the interrupt on the interrupt controller */
pAIC->AIC_ICCR = (1 << AT91C_ID_SSC0);

/* Configure the interrupt controller */
AT91F_AIC_ConfigureIt (pAIC,
AT91C_ID_SSC0,
AT91C_AIC_PRIOR_5,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
isrSSC0);

/* Enable the SSC_0 interrupt */
AT91F_AIC_EnableIt (pAIC, AT91C_ID_SSC0);

/* Get status; clear flags */
status = pSSC->SSC_SR;

/* Enable empty transmit/receive buffer interrupt */
AT91F_SSC_EnableIt (pSSC, AT91C_SSC_TXBUFE | AT91C_SSC_RXBUFF);

/* Configure PDC */
AT91F_PDC_SetNextTx ((AT91PS_PDC) &(pSSC->SSC_RPR),
(char *) sendBuffer, sizeof(sendBuffer));

AT91F_PDC_SetTx ((AT91PS_PDC) &(pSSC->SSC_RPR),
(char *) sendBuffer, sizeof(recvBuffer));


AT91F_PDC_SetNextRx ((AT91PS_PDC) &(pSSC->SSC_RPR),
(char *) recvBuffer, sizeof(recvBuffer));

AT91F_PDC_SetRx ((AT91PS_PDC) &(pSSC->SSC_RPR),
(char *) recvBuffer, sizeof(recvBuffer));


/* Enable the receiver and transmitter */
AT91F_SSC_EnableRx (pSSC);
AT91F_SSC_EnableTx (pSSC);

/* Enable PDC channels */
AT91F_PDC_EnableRx ((AT91PS_PDC) &(pSSC->SSC_RPR));
AT91F_PDC_EnableTx ((AT91PS_PDC) &(pSSC->SSC_RPR));

return (pSSC);
}


After that the interrupt service routine assigns the send and receive buffers everytime it is called.

And again, there must be something magic to get it going. Or is it simply wrong?

Regards
akuehn
.

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