Re: I2C trick?

Vladimir Vassilevsky wrote:
"larwe" <zwsdotcom@xxxxxxxxx> wrote in message
I can imagine you could do very funky things with voltage dividers to
ensure that the master could always assert its will over both I/Os
regardless of what the other end is trying to do, but this would
result in some horrible non-spec I2C implementation. I can't imagine
shipping such a hack.

There should not be a need for such complication. So far nobody suggested a
valid reason why exactly it is a bad idea to swap the SCL and SDA to
separate the I2C slaves. I tried to do that; everything worked like
expected. This could actually be a good trick.

This trick is on the same level as assuming things about freshly-
malloced memory or relations between the addresses of local variables in
a program C. It may work, but it's not guaranteed.

If I see that correctly, the line-swapped device will see a start
condition whenever the master sends a '1' bit followed by a '0'; it will
see a '0' bit during a direction swap (between master releasing SDA
after the last bit and slave pulling SDA for acknowledge), and a '1' bit
during inactive periods (between a stop condition and a start
condition). This means, it is possible to construct a valid transaction
that is seen as, say, a start condition plus 8 data bits by the
line-swapped device. That device may now start pulling its SDA (i.e. the
current SCL) to low as an acknowledge, and thus lock up the bus.

Sure it's unlikely. But I've already seen devices lock up I2C even when
doing protocol, so I would avoid that trick if I can. Who knows what
goofs lurk in this world's I2C implementations.


Stefan

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Relevant Pages

  • Re: I2C trick?
    ... see a '0' bit during a direction swap (between master releasing SDA ... current SCL) to low as an acknowledge, and thus lock up the bus. ... Seen by line-swapped device: ...
    (comp.arch.embedded)
  • Re: Probleme mit I2C-Verbindung
    ... Den kann es nur geben wenn ein zweiter Master auf den Bus zugreift. ... The data on the SDA line must be stable during the HIGH period of the ... The HIGH or LOW state of the data line can only change when ...
    (de.sci.electronics)
  • Re: I2C slave code example for an ATtiny26
    ... >>master is determined by the value written to the USIDR register. ... The a start condition is generated by the master by forcing the SDA low ... >than the USI. ...
    (comp.arch.embedded)
  • Re: value of SDA in acknowledge phase.
    ... I don't think that it's an issue of who is the master. ... drive it as "Z") during the ack bit. ... The SDA line has a pullup so that it ... > Acknowledge cycle from the slave.In this cycle what shold the master ...
    (sci.electronics.design)
  • Re: Probleme mit I2C-Verbindung
    ... ob es da irgendwo Probleme mit gegeneinander kämpfenden Ausgängen gibt ... (Glaube war das Ack, der Master gibt SDA ... 2/3 H-Pegel bei SDA) kann auch davon kommen, dass der Slave nur 3V hat, ...
    (de.sci.electronics)