DMA / bus architecture

Some question (apologies for the basic questions, as I am not much of
h/w, but attempting to analyse the s/w implementation - just a short
conceptual one-liner or some keywords will do):

a. In dual core/quadcore, there is only one system bus which is
shared among the 4 CPU - for Intel north-south bridge architecture,
right? But in AMD hypertransport the different parts (meaning
different address range) of the memory can be accessed at the same
time by different CPU? (NUMA?)

b. Supposed there are N h/w devices wanting to access the main mem
via DMA, so all of them have to go through a DMA controller for memory
mapping. So it is impt on the software or BIOs side to ensure that
the physical address allocated to these devices does not collide among
themselves, correct? Is this done in kernel and/or BIOs?

c. BTW, there is something called "AHB" - advanced high performance
bus - what is the difference from the normal system bus?

Thanks a lot.
.