Re: X-Mega AVRs are here!

Ulf Samuelsson wrote:
"David Brown" <david.brown@xxxxxxxxxxxxxxxxxxxxxxxxxx> skrev i meddelandet news:47c6f520$0$15000$8404b019@xxxxxxxxxxxxxxxxxx
John Devereux wrote:
linnix <me@xxxxxxxxxxxxxxxxxx> writes:

<snip>
It's fair enough that it's an 8-bit architecture, but they could have put a little effort into fixing the most glaring design flaws of the cpu. Why not drop the fmul* instructions that almost never get used, along with the rcall opcodes (I guess they are used by Forth systems, but I can't see they are much use to a C compiler), and add some of the features that would have made a real difference to the cpu power for C programming? Adding an X+q mode comparable to the Y+q and Z+q, and making R24:R25 a forth pointer register would be a big help. Support for (SP+q) addressing would be a benefit, although it would not be too important if it there was more if a forth pointer with W+q addressing modes existed. A method of atomically accessing the 16-bit stack pointer would be useful, however.

Which of course require a new compiler...

No, it would mean a *change* in the compiler. If little-used instructions had to be dropped to leave room in the instruction space for the additional features, then you break backwards compatibility. But that's hardly something new - small breakages occur with changes to the memory maps, the introduction of the 3-byte return stack, and the differences to the eeprom access methods for every new generation of AVR.

Taking advantage of the new instructions would mean a fair number of changes to compilers - but there would be no problem generating correct code.

The decision was made to not change the CPU core.


Obviously that's the decision - the AVR designers are not daft, and it's easy to see the advantages that changes like these would have. I therefore assume they felt improvements to the core would be too disruptive to the design or the tools.

As for making it entirely von Neumann, I think that's a bit too big a change - but it would have been perfectly possible to make the flash accessible in the data space as well (in the same way as the eeprom is now mapped into the data space). You'd need 24-bit pointers to access it, but it would still be a very useful feature.


The AVR core supports 16 MB dataspace and 8 MB instruction space.
I think that if the code was mapped to the upper 8 MB of the dataspace
there would be no conflicts.

Agreed.

Again, such a change would probably affect the compilers,
which was undesirable.


Again, it would not affect a compiler until the compiler added support for that sort of addressing. There is no harm in adding a feature - the only risk if you change remove features on which the tools depend (the view of flash in the dataspace would be in addition to the traditional lpm instructions).


It's also missing a CAN controller, and the SDRAM setup is a bit odd (it should be possible to get an 8-bit SDRAM bus using only three ports).


I assume that the fancy stuff will come in future chips.

Apart from that, it looks a very nice chip, which we will probably find use for. Maybe I can use it to drive my QVGA screen...

.

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