Re: Help me!

huxuelei630@xxxxxxxxx wrote:
On Feb 28, 8:45 pm, "Michael N. Moran"
<mnmo...@xxxxxxxxxxxxx> wrote:
huxuelei...@xxxxxxxxx wrote:
Hi, I have been developing a driver for plx9656 device.Now I want to use DMA to tranfser data from
Local Address to PCI Address.But I always got wrong
result.
You're not giving us much to work with. For example,
what is this "wrong result?"

There is a bit more to doing a DMA transfer than just setting up the DMA registers.

o Does the transfer complete (without errors?)
according to the register interface? o Are you
expecting/receiving an interrupt? o If the register
interface indicates completion, is the expected data
incorrect?

Working with PCI can be ... interesting, and there are
many details that need to be correct. On top of that,
processors that operate with PCI buses can add a few
layers of fun themselves (e.g. interrupt controllers,
virtual addresses and caches.)

If you want help, you need to give details.

Oh, I am sorry.I did not say that clearly.

My driver can transfer data,

Into a DMA source buffer?

and I can handle these data after I received a DMA DONE
interrupt.

What do you mean by "I can handle these data?"

Do you mean that you can still "see" the data
in the DMA source buffer after the transfer
is complete?

The data in the FIFO are like these: 0x00000001,
0x00000002, 0x00000003,...0x0001000.

What FIFO? Is the FIFO part of a peripheral?

In every FIFO interrupt , I should tranfser these data
from FIFO to another address.

That sounds like a typical operation to perform on the
receive FIFO of a peripheral.

I can transfer correctly when I use memory copy.

In other words, you can read the FIFO and copy
the contents to a receive buffer just fine with
no DMA. Correct?

But after I start the DMA, these transfered data would be
like these: 0x00000001, 0x00040001, 0x0000001,
0x00040001,......

I assume the DMA controller indicates that it completed
the transfer and that the DMA destination buffer contains
these values.

If that is the case, and if you have setup the DMA
controller correctly (source address, destination
address, count, etc.), and you have done your
physical-virtual-bus address mapping correctly that
the most likely problem is one of cache coherency.

You have not said anything about the type of processor
you are using or about its cache coherency protocol
with respect to the DMA controller.

Does the processor's data cache snoop the DMA
destination memory? If not you may need to manually
invalidate cache associated with the DMA destination
buffer.

IOW, what you may be seeing is stale data in your
cache.


--
Michael N. Moran (h) 770 516 7918
5009 Old Field Ct. (c) 678 521 5460
Kennesaw, GA, USA 30144 http://mnmoran.org

"So often times it happens, that we live our lives in chains
and we never even know we have the key."
"Already Gone" by Jack Tempchin (recorded by The Eagles)

The Beatles were wrong: 1 & 1 & 1 is 1
.

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