Re: Feasible to implement a router on a system on a chip?

Keith M wrote:
aubrey wrote:

I discovered that the MIPS architecture is widely licensed and used
frequently in common embedded applications. For example, the DI-525
router, hardware version C, uses a System on a Chip with the MIPS
instruction set, FLASH, and RAM. Lots of flash and ram, like 16Mb RAM
and 4Mb Flash (various posts cite different numbers).

I've often thought about buying some of these devices just to have a working platform. If you buy all that stuff separately, it would cost you a fortune. Those people hacking those devices are pretty crazy in their reverse engineering skills.

Yeah 16mb of ram and 4mb of flash is a lot of memory. However, if you compare it to today's serious routers(anything even remotely close to the OP's idea), it's not nearly enough. I just recently fitted a Cisco with 64MB flash and 256MB DRAM. It doesn't have the most complete feature set either...... and if you look at Cisco's memory roadmap, it will probably need upgraded by 2009. And this was in a router designed to handle T3 speeds. 45mbps.


I can see how you might have use for more RAM - storing bigger routing tables, ARP caches, connection trackings, and so on, as well as doing some packet buffering. But I have difficulty seeing how you would fill 256 MB with this sort of thing unless you are switching a lot of 10 GB lines with serious congestions - your aim in the router is to pass packets through without storing them, unless it is absolutely necessary (such as because of differences in line speeds). I certainly can't imagine what you'd want with 64 MB flash - even if you run a non-specialised kernel such as Linux on your router, the kernel, all the networking, routing and filtering code, and the basic configuration tools will fit in about 2 MB. Add another 2 MB for a fancy web interface if you want.
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Relevant Pages

  • Re: Feasible to implement a router on a system on a chip?
    ... instruction set, FLASH, and RAM. ... Lots of flash and ram, ... And this was in a router designed to handle T3 speeds. ...
    (comp.arch.embedded)
  • Re: Performance and Flash Pipelining on TI 28F12 DSPs
    ... > of "critical code" we could move to RAM. ... > from internal flash? ... Since the external RAM is as big as the internal flash, ... the timers and all other interrupts are shut off, ...
    (comp.dsp)
  • Re: [ANNOUNCE] Ramback: faster than a speeding bullet
    ... The fact is, enterprise scale ramdisks are here now, while ... enterprise scale flash is not. ... does not approach the write performance of RAM, ... My goal is not to replace RAM with flash, but disk with flash. ...
    (Linux-Kernel)
  • Re: Relocate from nor to ddr CE 5.0
    ... programmed into flash. ... but the image info says it belongs to ram. ... Your bootloader needs to have code that recognizes if the image is ... blt CODEINRAM ...
    (microsoft.public.windowsce.platbuilder)
  • XIP vs RAM
    ... Maybe the system can even get away with the next small size RAM ... Does anyone know if/what the premimum of the "K" Strata FLASH is? ... Also what are the steps needed to transition to a XIP OS? ... >>> My bootloader create a BINFS partition and an EXTENDED partition on ...
    (microsoft.public.windowsce.platbuilder)