Want to change your career? visit www.tiit.in

Hi Friend,

TIIT in association with Cadence Design Systems, University of
California and TTM Inc, is providing Certification course in VLSI
Desing Engineering.
Its a Part Time Course runs for a duration of 20 weeks (on Saturdays
and Sundays).

Courses are:
1) Logical Design Engineering
2) Physical Design Engineering.

The following tools from Cadence will be used for the training:

SOC Encounter
Encounter ATPG
Incisive Unified Simulator
RTL Compiler XL with BG and CTE
Virtuoso XL Layout Editor
Assura DRC/LVS
Assura RC
Virtuoso Schematic Entry
Nano Router
V-Strom
CellTic

For further query mail us to hydtraining@xxxxxxx

Regards,
TIIT.







.

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