Re: MC68020 Embedded System HW Reset Problem - Need Help
- From: Gene S. Berkowitz <first.last@xxxxxxxxxxx>
- Date: Thu, 29 May 2008 03:42:36 GMT
In article <483e1594$0$30498$4c368faf@xxxxxxxxxxxxxx>,
jflan@xxxxxxxxxxxxxxxxxxxxx says...
Hi -
I am hoping that someone could give some pointers as to how
and attack a reset (double bus fault) problem with an embedded
68020 board that was originally designed by HP in a piece of
test equipment that was mfg back in 1996. Since HP no longer
supports this equipment, I'm on my own. I do have the schematics,
however.
Problem:
There are times when the unit is powered up, that the 68020 will not
reset properly and simply locks up. Upon investigation, I have
determined that a double bus fault has occurred. There is a diagnostic
led on the HALT line that shows this to be the case. This lockup occurs
randomly on power up. I have two of these units, one unit exhibits this
problem where the other does not. Both units are running the same ver
of firmware that is mature. I'm convinced that the problem must be
hardware related.
What I've done:
The unit uses a TI supervisory reset part (TL7705) that has a reset
delay of 120mSec (I'v verified this). I've used a digital storage scope
to capture the rise time of the 5V power source, the reset line to the
68020, and the 68020 clock. All three signals behave as expected. The
osc starts up within about 5 mSec, the 5V supply within about 1mSec and
the reset pulse is approx 120mSec. However, about every dozen or so
power cycles, the processor will double bus fault and lock up. The osc,
by the way, is at 19.6MHz.
Originally, I thought that the power supply was coming up in a strange
manner or the TL7705 was malfunctioning, but I don't see it.
I need someone with 68000 HW design experience to give me some pointers
as to how and solve this. Any help would be appreciated.
Thanks
Jim
Check the rise time of the reset; it must be less than 1.5 clocks.
Does the board have an MMU, FPU or external cache SRAM? Such a device
may be issuing a bus cycle termination, which will result in BERR/HALT.
You might try disabling the internal cache by asserting CDIS.
Have you verified that the '020 is a 25 Mhz part, and not the 16 MHz
version, which _might_ be capable of running at 19.6 MHz?
--Gene
.
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