Re: arm9 memory throughput


"Nils" <n.pipenbrinck@xxxxxxxxx> wrote in message news:6fdfdvFb271lU1@xxxxxxxxxxxxxxxxxxxx
Hi folks.

I'm working on an ARM9 system (the DaVinci). Yesterday a workmate and I made some tests to measure the memory speed of
the system and we wonder a bit about the numbers we get.

In short the system during our tests looked like this:

* RAM is DDR2 at roughly 160Mhz
* The CPU is an ARM9 and runs at roughly 300Mhz
* We disabled all components that may access the RAM (e.g. video out, DSP ect).

In our tests we cleared a 3Mb chunk of memory using 32 bit writes and measured a troughput of 200 Mb/s. We tried
everything possible to improve the speed, e.g. unroll the loop, use store-multiple instructions ect. We always get the
200Mb/s. We can even put up to four nops between the writes and the numbers don't change.


Doing the same using DMA I get numbers around 1.3Gb/s on the same system.

I know that I never get the full theoretic memory throughput but 200mb/s is a lot less than we have expected. Now I
want to understand why this happends. Unfortunately I know s**t about memory interfaces, memory latencies and all the
other stuff.

Could somone please explain me what the memory and CPU does between the writes?

The ARM9 has a writebuffer which you need to enable by marking the
memory as bufferable/cacheable. After that the writes go straight into
the DDR2 command queue. It won't do merging of writes, and I don't
think the DDR2 controller will do so either, so you need to use STM with
an even number of registers to get the maximum bandwidth.

You could try loading each cacheline before overwriting it, if everything is
configured correctly you should get a similar result as the DMA.

Wilco


.

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