Re: Intel HEX format: extended segment address



On Aug 24, 2:40 pm, rickman <gnu...@xxxxxxxxx> wrote:
On Aug 24, 10:57 am, eliben <eli...@xxxxxxxxx> wrote:



On Aug 23, 9:41 pm, Coos Haak <chfo...@xxxxxxxxx> wrote:

eliben wrote:

<snip>

Thanks and I have a folloup question. In the same 'extended segment
format', how do CS and IP join to make the start address ? Is it
just CS << 16 + IP ?

CS << 4 + IP ;-)

CS << 16 would make a 4 GB address on a CPU with 20 address bits.
--
Coos

Oh, I see. Any good online reference on this topic ?
Searching Google for Intel, CS and IP doesn't bring much

I don't know about Intel Hex, but I know that there are no Intel
processors with a 20 bit address bus that use the Extended address
format. 20 bits is only 1 MB. The 80286 used the segment registers
to extend the address range of the 8086 to 20 bits. The 80286
extended this further to 32 bits.

Opps, I meant the 80386 extended this further to 32 bits.

The 386 chips may not have brought
out all 32 address bits, but there was a full 32 bit (4 GB) address
range and it was up to the designer to decide how the software address
would be mapped to the hardware address.

So I think Tauno was right, CS << 16 + IP.

Rick

.



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