AES encrytion (ASIC)

Hey folks , i need ur opinion about something :
To implement an AES decryption (CBC mode ) algorithm in ASIC , what
would be the best way to do it ? i mean among these architectures
which one do you choose and why :

* Basic iterative architecture
* Partial loop unrolling
* full loop unrolling
* Partia outer-round pipelining
* Full outerround pipelining
* Inner-round pipelining
* Partial mixed innerand outerroundpipelining
* Full mixed inner- and outer-round pipelining
* other ...

.

Relevant Pages

  • Re: AES decryption (ASIC)
    ... Partia outer-round pipelining ... Partial mixed innerand outerroundpipelining ... Full mixed inner- and outer-round pipelining ...
    (comp.arch.fpga)
  • AES decryption (ASIC)
    ... Partia outer-round pipelining ... Partial mixed innerand outerroundpipelining ... Full mixed inner- and outer-round pipelining ...
    (comp.arch.fpga)
  • Re: AES decryption (ASIC)
    ... i mean among these architectures ... Partia outer-round pipelining ... Partial mixed innerand outerroundpipelining ... Full mixed inner- and outer-round pipelining ...
    (comp.arch.fpga)
  • Re: AES encrytion (ASIC)
    ... To implement an AES decryption algorithm in ASIC, ... Partia outer-round pipelining ... Partial mixed innerand outerroundpipelining ... Full mixed inner- and outer-round pipelining ...
    (comp.arch.embedded)
  • Re: AES decrytion =>ASIC
    ... i mean among these architectures ... Partia outer-round pipelining ... Full mixed inner- and outer-round pipelining ... Highest clock rate? ...
    (comp.lang.verilog)