Xilinx bitstream encryption
Hello !
I would like to know the frequency used by Xilinx (Virtex 5) to
decrypt bitstream before configuration .
The decrypter is it slow with small area ? fast with big area ?
unfortunately it's not documented by xilinx .
Thank u for help
.
Relevant Pages
- Re: Virtex 5 bitstream encryption
... I would like to know the frequency used by Xilinx to ... decrypt bitstream before configuration. ... It decrypts at the same rate as the configuration clock. ... (comp.arch.fpga) - Re: Virtex 5 bitstream encryption
... decrypt bitstream before configuration. ... unfortunately it's not documented by xilinx. ... Do you mean ENcrypt when you wrote DEcrypt? ... (comp.arch.fpga) - Re: Virtex 5 bitstream encryption
... decrypt bitstream before configuration. ... unfortunately it's not documented by xilinx. ... Do you mean ENcrypt when you wrote DEcrypt? ... (comp.arch.fpga) - Re: Anybody understand this ISE 7.1 error, and what to do about it???
... > this code to a higher Virtex device. ... Why can't Xilinx make this clear to ... must account for that and fix functions that need SLICEM function ... old slices is defenetly fully clear ... (comp.arch.fpga) - Re: Spartan 3 documentation confusing...
... I *didn't* address the message to anyone at Xilinx. ... resistors are also on the JTAG pins. ... I still don't know if the configuration pullup resistors are ... (comp.arch.fpga) |
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