Re: 40 core embeddified processor
- From: Walter Banks <walter@xxxxxxxxxxxxx>
- Date: Fri, 26 Sep 2008 09:34:57 -0400
Martin Griffith wrote:
On Thu, 25 Sep 2008 20:57:09 +0100, in comp.arch.embedded "Wilco
Dijkstra" <Wilco.removethisDijkstra@xxxxxxxxxxxx> wrote:
I'm really out of my depth on this sort of thing, and was just
"Martin Griffith" <mart_in_medina@xxxxxxxx> wrote in message news:m6jnd4lp9dvf4e9o8i9o2g5toit897526k@xxxxxxxxxx
hmmm
http://ddj.com/hpc-high-performance-computing/210603583;jsessionid=MJC0UM1XWMCQOQSNDLOSKHSCJUNN2JVN
Definitely deserves a price for the wackiest microprocessor. You need a nop
after every addition, there is no subtract (just figure out how to do it using xor
and add), 16x16 multiply takes 40 instructions, only supports Forth...
Wilco
wondering what the pro's here think.
That's why I put a "hmmm" in my OP.
I wonder what the dev system is like, nope, can't be bothered to D/L
it
Martin
It is a weak instruction set. 64 words of ram and rom per processor
is strange. It isn't clear (to me) if the RAM is also the stacks. The
total ROM is 2560 for 40 processors which limits the size of
applications that can be described (I know instructions are packed
offset some by packing and execution order limits).
The web site doesn't make a compelling case for applications that
could effectively use this processor. Compare this processor with
the parallax Propellor for example. The parallax processor is far
more flexible
Walter..
.
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