Re: 40 core embeddified processor


"Walter Banks" <walter@xxxxxxxxxxxxx> wrote in message news:48DCE501.851F1683@xxxxxxxxxxxxxxxx


Martin Griffith wrote:

On Thu, 25 Sep 2008 20:57:09 +0100, in comp.arch.embedded "Wilco
Dijkstra" <Wilco.removethisDijkstra@xxxxxxxxxxxx> wrote:


"Martin Griffith" <mart_in_medina@xxxxxxxx> wrote in message news:m6jnd4lp9dvf4e9o8i9o2g5toit897526k@xxxxxxxxxx

hmmm
http://ddj.com/hpc-high-performance-computing/210603583;jsessionid=MJC0UM1XWMCQOQSNDLOSKHSCJUNN2JVN

Definitely deserves a price for the wackiest microprocessor. You need a nop
after every addition, there is no subtract (just figure out how to do it using xor
and add), 16x16 multiply takes 40 instructions, only supports Forth...

Wilco

I'm really out of my depth on this sort of thing, and was just
wondering what the pro's here think.
That's why I put a "hmmm" in my OP.
I wonder what the dev system is like, nope, can't be bothered to D/L
it

Martin

It is a weak instruction set. 64 words of ram and rom per processor
is strange. It isn't clear (to me) if the RAM is also the stacks. The
total ROM is 2560 for 40 processors which limits the size of
applications that can be described (I know instructions are packed
offset some by packing and execution order limits).

The return and data stack are separate and have 9 and 10 entries.

The ROMs contain library calls for most basic of operations (like subtract
or multiply).

The 64-word RAMs probably give around 128 instructions after all the packing
losses, required nops and inline literals. Given each instruction does very little
this is not much at all.

The web site doesn't make a compelling case for applications that
could effectively use this processor. Compare this processor with
the parallax Propellor for example. The parallax processor is far
more flexible

The Propellor is pretty odd as well (2 operands, 9-bit direct memory address)
and also uses an unconventional programming language. Personally I'd prefer
a fully featured core with single cycle instructions capable of running C.

Wilco


.

Relevant Pages

  • Re: <=>
    ... hmmm... ... (I'm running this in GRDB, so that i'll stop at the instructions immediately ... now let's try the other set of instructions... ... (i'll just nop out the cmp) ...
    (alt.lang.asm)
  • Re: 40 core embeddified processor
    ... Definitely deserves a price for the wackiest microprocessor. ... You need a nop ... there is no subtract (just figure out how to do it using xor ... That's why I put a "hmmm" in my OP. ...
    (comp.arch.embedded)
  • Re: Multi-byte "NOP"s
    ... multibyte nop instructions. ... and preceeding instructions do not use that same ... register, you can use EAX, EBX, ECX, EDX, ESI, EDI ...
    (comp.lang.asm.x86)
  • Re: 40 core embeddified processor
    ... Martin Griffith wrote: ... and add), 16x16 multiply takes 40 instructions, only supports Forth... ... That's why I put a "hmmm" in my OP. ... Thanks for the parallax Propellor pointer, ...
    (comp.arch.embedded)
  • Re: 40 core embeddified processor
    ... and add), 16x16 multiply takes 40 instructions, only supports Forth... ... That's why I put a "hmmm" in my OP. ... applications that can be described (I know instructions are packed ... the parallax Propellor for example. ...
    (comp.arch.embedded)