Re: 40 core embeddified processor

On Sep 26, 4:47 pm, "Wilco Dijkstra"
<Wilco.removethisDijks...@xxxxxxxxxxxx> wrote:
The Propellor is pretty odd as well (2 operands, 9-bit direct memory address)
and  also uses an unconventional programming language. Personally I'd prefer
a fully featured core with single cycle instructions capable of running C..

I had high hopes for the Propeller until I read the data *** and
discovered its limitations.

In addition to the unconventional programming language (Spin), it also
lacks in the following areas:

* Only 2K of RAM per cog (32K RAM/ROM main memory is only accessible
in interpreted Spin code)
* No integrated peripherals (except for timers and GPIO). Everything
else (e.g. I2C, SPI, ADC, USART, etc.) has to either be bit banged or
added externally
* No JTAG debug support. This is a big one for me. The Parallax
development platform (Propeller Tool) has no debugging capabilities
(single step, breakpoints, etc.)
* No interrupts, although the workaround here is to dedicate one or
more cogs to polling for events
.

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