Re: Hardware handholding
- From: Paul Carpenter <paul@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Tue, 4 Nov 2008 01:22:06 -0000
In article <ZqadnUe7ZdsD7ZLUnZ2dnUVZ_uudnZ2d@xxxxxxxxxxxx>, mitakeet@sol-
biotech.com says...
You can easily find uC with 50 I/Os. Two of them is far cheaper and
easier to deal with then FPGA. Alternatively, a uC with a simple
CPLD.
I thought that you could get FPGAs for not much more than twice that of a
CPLD and that it was reasonable to get a 100 pin FPGA for $100 or less.
Did I do a poor job of research or is $100 reasonable? At present, I only
need a single prototype of the hardware and presuming the chip idea works
the relative volume of the embedded hardware will be several orders of
magnitude less than that of the chip, so $100 ea. for several FPGAs is not
a significant issue.
I think you need more details by first checking out some ball park
pricing and working out some rough complexities required first. Actually
get some real figures to get an idea of what you want.
You do not seem to have a handle of the costs of making your
prototypes and incorporating FPGAs, soft cores and the like.
But, first of all, you need 100 amplifiers to bring the nA and nV up
to 1 to 2V.
Can the amplifiers be something as simple as some transistors on a PCB?
They could be, if you want something potentially drifting with
temperature, age, and potentially with low voltage and current input
picking up all sorts of stray interference as well.
This looks like a lot of work without a lot more details to work on.
As others have said the FPGA is not your weak point the analog
front end is. Which if that is not right means the rest of it might as
well be made of chocolate
You are really asking for a custom analog chip.
I know that ASIC is the way to go, but prototyping those is definitely out
of my budget. For a successful commercial product I expect to embed most
of the control circuitry on the same chip, which should mitigate much of
the concern.
A lot of ASICs start off as prototype circuits, then go through various
design phases to become an ASIC.
One of my customers is a design house and manufacturing for ASICs
with customers all over the world and all sorts of requirements.
Some of these have 10-20 year lifespans which involve things like
respinning the ASIC every 8-10 years as manufacturing processes
become obsolete.
Thanks again for your help!
--
Paul Carpenter | paul@xxxxxxxxxxxxxxxxxxxxxxxxxxx
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