Re: W65C02S, Z80, 80C31 or other legacy processor?

On Mar 29, 3:20 pm, -jg <Jim.Granvi...@xxxxxxxxx> wrote:

Perhaps we have better sourcing, or at least different... the mega8 is
a bit less than $1.00 in 30pc qty for us. I'm sure in the millions
both parts are more or less free, but not at these volumes.

Certainly sounds like special sourcing. Who is actually selling 30pcs
for sub $1 ?

I have the vendor's name bookmarked at work, but it is a Chinese OEM
that is already buying the parts for use in other applications. I know
Atmel's production qty price is considerably lower still.

60Hz composite video would be viewable on most PAL TV sets with a

Only if they were Dual PAL/NTSC capable - but anyway,

I used to live in a PAL country, and when I left (1999) all of the
sets were capable of so-called "PAL-60" with a large majority also
being capable of autodetecting actual NTSC with either 3.58 or 4.43MHz
color.

PAL monochrome is not a big jump

It's only a jump of software in fact, I wouldn't have much trouble
tweaking the display controller firmware for this purpose.

Why would the teaching material be non-portable ?

Can't get into that in detail, yet. Suffice it to say that it is
specifically written and intended for a US audience and might possibly
be perceived as jingoistic to foreign readers. Of course, there's no
reason why it couldn't be translated.

More of an issue is VGA, which is a good idea, but was off my list
due to a much higher ideal dot clock.

I've done the gfx resolution I describe in an MSP430F2012, at VGA
syncrates (driving a "virtual" 640x480 display). Don't think I will
have trouble with it on an Atmel CPU. I will use the SPI peripheral to
output pixels, so the core only has to service 1/8th the data rate,
with no shifting or masking necessary.

The host will use sync signals to determine when it's safe to send the
next byte of command data. You've just reminded me, though, of the
reason I was going to use async serial as the interface between the
two rather than SPI - I'm already using SPI for video output, and I
need a hardware-buffered interface obviously, since the display
controller can't bit-bang anything while it's outputting display data.

This ground is very thoroughly trodden; if you google for "AVR VGA" or
"AVR NTSC" you will see several such projects though unrelated to
mine.

Point taken, but this model is what most cameras, and MP3 players use.
- and there are many mllions of those...

.... and I myself have several Chinese MP3 players that won't enumerate
properly on some operating systems. Grrrr.

Anyway, SD gives you a safety net ? - and someone else can do the
USB drivers... you are open-sourcing this ?

It's the intention. It might get messy if we have to include some
third-party IP, the client is still looking at that. Would very much
not want to have binary blobs in the product.

Qualitatively different. It does not show the data flowing and the
buses (control as well as data and address) toggling during the act of
reading and writing data.

but how will you actually achieve that ? Mega cannot execute from RAM,

Exactly, but as I tried to point out in my summary email (I guess I
didn't state it explicitly...) the user will not "know" this is an
AVR, the CPU will just be "CPU" and the accessible APIs will be the
6502 machine language monitor and BASIC interpreter - plus CHIP-8 if I
can manage it.

you can only show data fetch, but data access  will be too fast on WRN/
RDN, so you need then additional sw-emulation to slow the bus way-

See above. Single-step down to the machine cycle level is a software
feature only since it's all emulation.

With 128K & three emulations, it is already going to be complex :).

Not unless the user intentionally breaks the "encapsulation". By which
time I would say they have graduated with flying colors!
.

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