Re: ROM wait states

RIYA wrote:

can anyone explain me to calculate the wait states needed?
Suppose we are using 120 nanosecond ROMs, which have valid data on the bus
120 ns after the falling edge on the Output Enable line with a clock rate
of 25 MHz (which means a clock cycle of 40 nanoseconds). How many wait
states must the microprocessor insert into each bus cycle that reads from
the ROM?

Maybe 3 wait states? But you have to check the timing diagrams of the
datasheets of the ROM and the microprocessor. "wait state" doesn't mean
always the same and there could be other timing constants, e.g. how long
the ROM needs to release the address bus after chip select release. Draw a
timing diagrams on a big paper for your system and verify it with the
datasheets. If you want to document it, this is a nice font for it:

http://www.pcserviceselectronics.co.uk/fonts/

--
Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
.

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