Re: MAX11043 - trying to avoid interrupts at 200kHz...

On Dec 16, 12:41 pm, "Steve at fivetrees"
<st...@xxxxxxxxxxxxxxxxxxxxx> wrote:
I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
output). It has an end-of-conversion pin, which when active means that a
bunch of data is available to read via SPI.

Which is fine, except I want to run this baby at 200kHz (ish). Which means
that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages - not
one sample at a time ;) - so needs to be aggregated into main memory for
despatch (with some extra room for Ethernet delays, say 1s-worth). The CPU
does have a SPI DMA subsystem, but needs to be primed in code...

So why is that a problem ?


So - one way of solving this is to find (or design) a FIFO with SPI in, and
SPI (or any other form of DMA-able CPU subsystem - again seems nuts to
shuffle this one byte at a time) out. Short of a Lattice IP core, I'm
finding nothing off-the-shelf. Could design some logic to use a parallel
dual-port FIFO, but seems wrong: I'd have to convert from SPI to parallel on
the way in, and the reverse on the way out.

I've asked Maxim the obvious question: how do I interface to this thing?
They've not been able to help.

Most SPI parts are designed sensibly - so they can stream data once
initialized.

If configure of DMA is too complex, then a few lines of code should
run a FIFO in SW, in the interrupt.

You could use a CPLD, but normally such a step is only needed if you
have a real brick-wall problem, like (eg) a SPI that only receives 16
bits and a SPI ADC that only sends 12 bits...

-jg


.

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