Re: MAX11043 - trying to avoid interrupts at 200kHz...

In article <-eGdnbKi0oh5ObXWnZ2dnUVZ8hOdnZ2d@xxxxxxxxx>,
steve@xxxxxxxxxxxxxxxxxxxxx says...
"Paul Carpenter" <paul@xxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:MPG.25924824fda56715989747@xxxxxxxxxxxxx
In article <OZGdnW0K7fNcg7XWnZ2dnUVZ8t6dnZ2d@xxxxxxxxx>,
steve@xxxxxxxxxxxxxxxxxxxxx says...
I'm trying to interface to a MAX11043 (4-channel synchronous ADC with SPI
output). It has an end-of-conversion pin, which when active means that a
bunch of data is available to read via SPI.

Which is fine, except I want to run this baby at 200kHz (ish). Which
means
that using the EOC pin as an IRQ input is fairly nuts. (CPU is an AVR
AT32UC3A.) The ADC data will be shipped out, raw, in Ethernet messages -
not
one sample at a time ;) - so needs to be aggregated into main memory for
despatch (with some extra room for Ethernet delays, say 1s-worth). The
CPU
does have a SPI DMA subsystem, but needs to be primed in code...

So why not do the code for SPI with DMA?

If you are sending data in Ethernet packets, you will be buffering the
data to build up your packet size, so what is the problem with filling
buffers using DMA?

Maybe I wasn't clear enough - the problem is that, while the CPU can do SPI
under DMA control, the DMA sequence is initiated in software. I can see no
way at all of starting an SPI DMA sequence in hardware, which was my
original expectation. Therefore we either have to trigger an IRQ on EOC, and
start the DMA sequence in the ISR, or design an SPI FIFO which would
generate IRQs less frequently and cause larger chunks of SPI data to be
transferred (or indeed DMA the data in some other way). I'm hoping I'm
missing something simpler.

However considering what has to be done (from my limited reading of
AT32UC3A datasheet) -

Initialise all peripherals (preload all registers)

Start conversion set CONVRUN

EOC interupt Start DMA of 4 x 16 bit transfers.
(hit the go bit for the channel)

End of DMA INTERUPT reset pointers and counters
Flag when buffer full for rest of app
Probably use double buffering to allow next block
to be started if still here.

The real problem is not the EOC, but that the DMA controller does not
seem to be able to be set for SPI RECEIVE to do repeated blocks of
data (due to no obvious hardware trigger/pause), until a transfer count
number of blocks are done.

This then means there is more in the End of DMA transfer interupt in
processing buffer handling and reseting DMA registers, so I can see
some of the issues.

You actually end up with 400kHz of interupts, before anything else
in your system.

I also could not see any obvious way to do parallel DMA from external
device/FIFO, which may have simplified things.

I've asked Maxim the obvious question: how do I interface to this thing?
They've not been able to help.

It may be they did not understand your question.

Heh. I actually just asked for any other data on the MAX11043, such as
application notes... I was told there is no other data.

I actually think the problem is more the AVR32 and how it does SPI
under DMA due to hardware trigger issues.

On other micros I would either externally do SPI receive and use
DMA with burst mode transfers, or a FIFO for DMA at half full.
Alternatively dual ported RAM, which the SPI receive hardware
directly does its own 'dma' into, with dual buffering and interupt
on buffer full or error.

--
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