Re: MAX11043 - trying to avoid interrupts at 200kHz...

"Tom" <tom@xxxxxxxxxx> wrote in message
news:DAfWm.107031$gg6.61273@xxxxxxxxxxxxxxx
In article <-eGdnbKi0oh5ObXWnZ2dnUVZ8hOdnZ2d@xxxxxxxxx>, "Steve at
fivetrees" <steve@xxxxxxxxxxxxxxxxxxxxx> wrote:
Maybe I wasn't clear enough - the problem is that, while the CPU can do
SPI
under DMA control, the DMA sequence is initiated in software. I can see no
way at all of starting an SPI DMA sequence in hardware, which was my
original expectation.

I understand that there is no way to hardware-trigger the DMA in SPI
master
mode but what if you configure the SPI for slave mode and then start the
DMA?
Will the DMA wait until some external source (like a counter) starts
generating CLK pulses and shifting the data from the ADC to the CPU? If it
will, then all you need to add is a counter that is triggered by EOC and
generates 64 CLK pulses before waiting for another EOC.

You, sir, are a blinking hero. That idea not only has legs, it works out
even better than that. The EOC signal goes false when all bits are shifted
out, so there's no need for a counter. Basically, this method adds the
capability to be an SPI master to the MAX11043, which was the simplifying
insight we were lacking (and which we've spent the afternoon kicking
ourselves about). It's really quite beautiful.

There's one little remaining bit of kludginess - while the MAX11043 has data
in, data out (and clock in), the AVR has MOSI and MISO (and clock in/out).
MISO and MOSI reverse directions when changing from master to slave, but
that's ok, I can deal with that in hardware (driven by a pair of GPIO pins).
We do need to talk to the MAX11043 too, to configure it...

We still need to prove that a 16-bit DMA transfer is complete before the
next 16 bits are shifted in (the max the AVR can handle in one chunk), but
we're working on that.

Thanks, Tom, I owe you a pint.

Steve
--
http://www.fivetrees.com


.

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