DMA losing sync on ST ARM processor

I'm using an STM32F103VB, and one of the things that I'm doing is doing a
set of ADC reads which are then being transferred via DMA to a buffer.

For some reason, when I'm debugging the DMA transfer gets scrambled:
channel 0 ends up where channel 1 is supposed to go, channel 1 where
channel 2 should be, on up the line until finally the last channel gets
written to channel 0.

I have the code set up for the ADC to run in "scan" mode, with the DMA
(theoretically!) sucking the data off and putting it into memory.

Furthermore, I have the ADC ISR set up so that on an end of conversion
interrupt (which is only supposed to happen at the end of the scan in
scan mode) the DMA engine gets reinitialized to point to the base of the
memory array it's supposed to write to.

Does anyone have any obvious clue to what I'm doing wrong? Does ST have
any good bits of sample code that I've missed?

Thanks in advance.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com
.

Relevant Pages

  • Re: DMA losing sync on ST ARM processor
    ... set of ADC reads which are then being transferred via DMA to a buffer. ... when I'm debugging the DMA transfer gets scrambled: ... channel 0 ends up where channel 1 is supposed to go, ... I have the code set up for the ADC to run in "scan" mode, ...
    (comp.arch.embedded)
  • Re: DMA losing sync on ST ARM processor
    ... when I'm debugging the DMA transfer gets scrambled: ... channel 0 ends up where channel 1 is supposed to go, ... I have the code set up for the ADC to run in "scan" mode, ... interrupt coming from the DMA controller on the completion of a set of ...
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