Re: WSJ article on software liability

From: CTips (ctips_at_bestweb.net)
Date: 03/01/05 

Date: Tue, 01 Mar 2005 15:49:14 -0500

Martin Brown wrote:
> Traveler wrote:
>
>> In article <slrnd28j7t.1824.willem@toad.stack.nl>, Willem
>> <willem@stack.nl> wrote:
>>
>>> Traveler wrote:
>>> ) well-known in the industry. Even the most ardent champions of "no
>>> ) silver bullet for software reliability", acknowledge that hardware
>>> ) systems are orders of magnitude more stable than software systems of
>>> ) equal complexity. You are out of your league.
>>>
>>> Quotes please ? I have yet to see anyone but you state that hardware
>>> is more stable than software *of* *equal* *complexity*.
>
>
>> I
>> make it a point on my site and in my messages on this forum to compare
>> software logic with hardware logic. A software system with comparable
>> logical complexity to a hardware system is much more prone to logical
>> failures.
>
>
> But that is a parody of the situation. A lot of hardware these days is
> developed using simulators and high level design languages like VHDL
> that are not all that different from software compilers for Ada, C or
> Pascal. eg
>
>
http://tech-www.informatik.uni-hamburg.de/vhdl/doc/cookbook/VHDL-Cookbook.pdf

Bzzt... try again. You can code in VHDL as you would in C, but it
*won't* synthesize (i.e. the tools will not be able to generate hardware
for from that code).

Consider the case where we're looking for a non-zero element in an array.
    int any_non0( int a[8] )
    {
      int i;
      for( i = 0; i < 8; i++ )
        if( a[i] != 0 )
          return 1;
      return 0;
    }
The equivalent code in VHDL won't synthesize.

Remember that VHDL is intended as a hardware description language. So we
have to describe the actual hardware. Assume we're use 8 comparators and
then or-ing the results together. The VHDL we write would be as though
we wrote the following in C:
    int any_non0( int a[8] )
    {
      return ( a[0] != 0 ) | (a[1] != 0) | (a[2] != 0) | ( a[3] != 0) |
              ( a[4] != 0 ) | (a[5] != 0) | (a[6] != 0) | ( a[7] != 0);
    }
See how many opportunities there are for mistakes compared to the
standard C code? And note how difficult it will be to change the
VHDL-like code to check for non-0 of 7 or 9 elements, compared to
changing the code in the original C.

Now, VHDL has an equivalent of a for (the generate-for statement) which
would let us write code closer to the original C. But, most designers
don't use it much, because some tools don't handle generates very well.
[Remember, the VHDL is used not only for synthesis but for things like
formal verification etc., so multiple tools need to consume the VHDL].
Also, verilog didn't have a generate till the 2001!

Actually, it gets worse. A better version of the hardware would or the 8
values together, and then do the compare. While I don't know what the
tools today are capable of, I wouldn't trust the synthesis tool to
recognize this optimization. So, the code which one writes would be:
    int any_non0( int a[8] )
    {
      return (a[0] | a[1] | a[2] | a[3] | a[4] | a[5] | a[6] | a[7])!=0;
    }

So, for the same problem, the VHDL ends up being more complex.

>
> I hate to admit it but hardware engineers are more disciplined and
> better at code reuse than software engineers.

Not my experience at all. There is a certain amount of reuse in hardware
of IP blocks, but then there is a certain amount of reuse in software of
library functions.

And as for discipline.... the less said the better.

Relevant Pages

  • Re: FPGA VHDL in research environment
    ... Unfortunately I am completely new to VHDL so I am not sure what I ... Hardware has to be modeled - not programmed. ... VHDL is more like a CAD program even it looks like a programming language. ... The register level is important, ...
    (comp.lang.vhdl)
  • Re: Freeware 32bit command line hardware detector?
    ... for the purpose of creating a hardware independent Windows XP Ghost ... or whatever I could compare against) and then the ... script would know which HAL to copy into windows\system32 and then the ...
    (microsoft.public.windowsxp.general)
  • Re: introducing FPGAs
    ... provide a means of creating VHDL code. ... there is also the issue of the hardware that would be used in this lab/ ... my bit to improve the quality of what we are offering our students. ... combinational logic implementation. ...
    (comp.lang.vhdl)
  • Re: Correct VHDL?
    ... I want to implement the following C++ code in VHDL ... with no libraries linked in. ... It's a hardware description ... Writing higher level, more abstract code, is a ...
    (comp.lang.vhdl)
  • Re: IBM in talks to buy Sun
    ... To compensate for slower speeds, double the number of file servers behind a load-balancer, and ultimately the number of disks. ... To compensate for lower reliability (but consumer grade hardware is getting better), assume a doubled disk replacement rate in the RAIDs. ... Parallelism in various forms (multiprocessors, load-balanced clusters, RAID, and so forth) make consumer grade hardware able to "add up" to be equivalent to higher-grade hardware. ... It'd be interesting to compare that hard data to comparable data for high-end drives - except oh wait, there isn't any, because nobody's ever used them in that kind of volume. ...
    (comp.lang.java.programmer)