Re: Data Directed Program Execution

alan-spiderman@xxxxxxxxxx wrote:

Gene>> "dataflow architectures"

Yes!! Thank you! Now that I have the right term for it, I see it all
over the web.

But, as Wikipedia says
(http://en.wikipedia.org/wiki/Dataflow_architecture): "No commercially
successful computer hardware has used a dataflow architecture". So I
don't think I'm going much farther with this. I am going to keep
playing with it in my spare time. It might be possible to get a little
closer to the "ideal" in a VM than it was in real hardware.

There is something similar to that at a lower level: asynchronous
logic design, in which there is no master clock which times the
logic. Basically each change in data comes with a signal that
indicates new data. It is the same concept, but on the level of logic
functions and maybe add / multiply / move, etc. The potential
benefits are that the logic uses less power, since a constantly
running clock signal (used in normal logic design) causes energy
dissipation as it continually charges and discharges the parasitic
capacitance of clock lines going to many logic gates, even though most
gates have no functional change on any given edge. In an asynchronous
design, the inputs are unchanged until new data arrives to be
processed, thereby lowering system power. Also, the switching noise
appears less correlated, since signals arrive at different times to
different gates, thereby cutting down on EMI.

--
Thad
.

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