Re: A Problem with makefile.

<prasadjoshi124@xxxxxxxxx> wrote in message
news:1164817267.853818.131820@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
i All,

I am trying to write a make file with the following specifications.

[Prasad@rsharma dir_make]$ pwd
/home/Prasad/programs/c/lsp/dir_make

[Prasad@rsharma dir_make]$ ls
add include main.c Makefile sub

Now, here main.c uses a function present in add/add.c and sub/sub.c.

I have written this makefile

[Prasad@rsharma dir_make]$ cat Makefile
SUB_DIRS := add sub
all:
@for d in $(SUB_DIRS) ; do \
( \
cd $$d ; \
make ; \
) \
done
OBJ_FILES=$($(foreach dir,$(SUB_DIRS),$(wildcard $(dir)/*.o)))
echo $(OBJ_FILES)
gcc main.c -o main -I $$PWD/include $(OBJ_FILES)
[...]

It seems that OBJ_FILES variable is not getting set properly.

I believe I see your problem...

I assume those lines after "done" start with a tab character,
which tells make to execute them as shell commands. So, even
if OBJ_FILES got some kind of value out of the assignment, it
be immediately thrown away since each of these lines is executed
in a new process.

You need to move the setting of OBJ_FILES out of there so it
doesn't look like a shell command to be executed. Something
like this:

SUB_DIRS := add sub
OBJ_FILES=$($(foreach dir,$(SUB_DIRS),$(wildcard $(dir)/*.o)))
all:

-Wm




.

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