Re: Java’s Future Lies In Mobile?

On 03/14/2011 03:53 PM, Arne Vajhøj wrote:
I would not expect Moore's law broken i 2015.

They can still shrink a little bit, number of cores will
increase, size of caches will increase (the cost of a cache
miss is equivalent to a lot of instruction using cache), smarter
CPU's (maybe even more CISCy), fundamental new technologies
(even though I suspect they will not be generally available
as soon as 2015).

Moore's Law states simply that the *number of transistors* on a chip doubles every 2 years (implicitly referring to roughly same-size chips, so perhaps transistor density doubling would be a more precise wording). Improving ISAs would certainly help in terms of performance, but most of the research I've seen recently has focused on helping parallelization, not improving serial code execution.

--
Beware of bugs in the above code; I have only proved it correct, not tried it. -- Donald E. Knuth
.

Relevant Pages

  • Re: surprising pthread problem
    ... I don't think you will see any speedup using this technique. ... The cost of creating threads is not zero. ... available cores so there is always the cost of switching. ... Assuming that the destination matrix is in the same cache line ...
    (comp.unix.programmer)
  • Re: surprising pthread problem
    ... The cost of creating threads is not zero. ... available cores so there is always the cost of switching. ... Assuming that the destination matrix is in the same cache line ...
    (comp.unix.programmer)
  • Re: =?windows-1252?Q?Java=92s_Future_Lies_In_Mobile=3F?=
    ... They can still shrink a little bit, number of cores will ... size of caches will increase (the cost of a cache ... miss is equivalent to a lot of instruction using cache), ... so perhaps transistor density doubling would be a more precise wording). ...
    (comp.lang.java.programmer)
  • Re: Multicore problem
    ... causing more cache misses than if a single task/core is active? ... it takes several cycles to read or write ... If you have to read from memory, ... cores to 4 cores, you can double the size of the queue waiting for a ...
    (comp.lang.ada)
  • Re: Lockfree_mpmc and scalability ...
    ... it makes it much slower cause the cache to cache tranfer is costly ... on single thread and four threads but it doesn't scale with four threads. ... So the following parts are sharing variables between the cores and making ...
    (alt.comp.lang.borland-delphi)