Re: Next Generation of Language

mark.hoemmen@xxxxxxxxx wrote:

Intel's proposed 80-core architecture will have DRAM attached to each
core -- sort of how Cell has "local stores" attached to each SPE.
That's how they plan to solve the BW problem -- amortize it over all
the cores.

Don't we call that `cache' normally? (yes, I know, they'll be *big*
caches, but only big by today's standards, in the same sense that
today's machines have as much cache as yesterday's had main memory.)

.

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