Re: Next Generation of Language

On 11 Jan 2007 13:03:57 -0800, "Tim Bradshaw" <tfb+google@xxxxxxxx>
wrote:

mark.hoemmen@xxxxxxxxx wrote:

Intel's proposed 80-core architecture will have DRAM attached to each
core -- sort of how Cell has "local stores" attached to each SPE.
That's how they plan to solve the BW problem -- amortize it over all
the cores.

Don't we call that `cache' normally? (yes, I know, they'll be *big*
caches, but only big by today's standards, in the same sense that
today's machines have as much cache as yesterday's had main memory.)

Well, on Cells the private memories are not cache but staging memories
.... the main processor has to move data into and out of them on behalf
of the coprocessors. It's very similar to the multi-level memory
system used on the old Cray's where the CPU had to fetch and organize
data to feed the array processors and store the results back to the
shared main memory.

AFAIK, no one has tried to offer a hardware solution to staging
computations in a distributed memory system since the KSR1 (circa
1990, which failed due to the company's creative bookkeeping rather
than the machine's technology). Everyone now relies on software
approaches like MPI and PVM.

George
--
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