Re: Automatic parallelization - was Re: LISP Object Oriented?

On 30 Jan 2007 01:43:18 -0800, "Tim Bradshaw" <tfb+google@xxxxxxxx>
wrote:

On Jan 30, 8:34 am, George Neuner <gneune...@xxxxxxxxxxx> wrote:
On 29 Jan 2007 09:06:34 -0800, "mark.hoem...@xxxxxxxxx"

We've already got quad-core general purpose CPUs and larger n-ways on
the horizon.

We already have 8-core CPUs in general use, outside of x86, and have
had for around a year.

I would hardly call UltraSparc a "general use" CPU - it has what now?
0.05% of the market. I concede that it is "general purpose".

The vast majority of multicore machines are dual or quad.


I think it's fairly clear that pretty much any vanilla 4-core CPU will
be starving for memory almost all the time (in particular the kinds of
things that intel and AMD will be pushing this year).

I don't think it's clear at all.

Starvation characteristics depend on the cache performance (frequency
of stall) and the CPU pipeline depth (how long to recover) - there is
nothing "vanilla" about it.

Studies done in the early 90's showed that, with appropriate caching,
from 12-16 CPUs could be supported a from shared memory system without
starvation.

In the late 90's CPUs had made such a huge leap in performance
relative to memory that the number of CPUs that could be served
without starvation dropped to under 4. But this is no longer the
case.

Memory has made a huge comeback in the past few years while core
speeds have remained stable. A modern 2GHz core running over PC-6400
actually has more memory bandwith available than did a 500Mhz R3000
over FPM in 1990.

The impact of a stall is greater on the modern core, but multiple
issue mitigates this somewhat because only the dependent pipeline(s)
need be stalled - unrelated processing can continue.

I am not aware of any recent academic studies on starvation in close
couple shared memory systems - nearly everyone lost interest after the
"Memory Wall" paper was published in the mid 90's.

George
--
for email reply remove "/" from address
.

Relevant Pages

  • Re: 2nd CPU on a Sun Blade 2000 problem
    ... memory) and left the original in the '0' slot? ... will only find in a Sun Fire 280R (uses the same CPUs and system board, ... but is a rack mount server, and the RSC card allows "LOM" (Lights Out ... framebuffer slot -- and there is no way to use a UPA framebuffer in the ...
    (comp.sys.sun.hardware)
  • Re: Lies, Damn Lies and Statistics...
    ... I've never looked at the source code of either IDS or DB2. ... binds sessons to engines hence if the engine is busy ... dynamically add shared memory segments on Linux. ... CPUs, as it sees fit. ...
    (comp.databases.informix)
  • Re: Best FPGA for floating point performance
    ... > the problem with highly threaded cpus is that they are not very good ... SW performance today as well as the cpus memory systems that don't like ... also FPGA P/R have no locality at all. ... Sparc in its Niagara form will serve their needs better than any x86, ...
    (comp.arch.fpga)
  • Re: Intel details future Larrabee graphics chip
    ... for dinky little SMP systems of 4-8 cores. ... Why multi-thread *anything* when hundreds or thousands of CPUs are ... video CPUs using fancy memory and generics doing the grunt work. ... Duo, and never get trojans, memory leaks, any of that. ...
    (sci.electronics.design)
  • Re: what is the meaning of registers,internal memory?
    ... Unlike RAM, these little scratch pads as I mentioned are tucked away ... RAM = Random Access Memory, ... number of CPUs on a memory bus, and eliminates the bottlenecks with many ... NUMA systems are not clusters however, ...
    (comp.lang.asm.x86)