Re: 6502 FPGA core
- From: Frank Buss <fb@xxxxxxxxxxxxx>
- Date: Mon, 28 May 2007 18:09:40 +0200
Sven-Olof Nystr|m wrote:
It seems to me that a more natural way to represent this code in a
Lisp program would be to use some form of syntax trees.
For example, the VHDL statement
if q = x"00" then z_flag <= '1'; else z_flag <= '0'; end if;
could be represented with this tree:
(if (= q #x00)
(<= z_flag #\1)
(<= z_flag #\0))
Producing VHDL code from the tree representation should be
straight-forward.
Thanks, this is a good beginning. But my hope was something more abstract,
e.g. like Esterel:
http://www-sop.inria.fr/esterel.org/home.htm
but in Lisp. My idea is to write algorithms in a more natural way than with
state machines and then it will be compiled into VHDL (even better would be
into EDIF netlists).
--
Frank Buss, fb@xxxxxxxxxxxxx
http://www.frank-buss.de, http://www.it4-systems.de
.
- Follow-Ups:
- Re: 6502 FPGA core
- From: Sven-Olof Nystr|m
- Re: 6502 FPGA core
- Prev by Date: LW 5 FLI issues on OS X
- Next by Date: Re: LW 5 FLI issues on OS X
- Previous by thread: LW 5 FLI issues on OS X
- Next by thread: Re: 6502 FPGA core
- Index(es):
Relevant Pages
|
|
