Re: Bootstrapping ANSI CL

On Jun 14, 6:21 pm, C Y <smustude...@xxxxxxxxx> wrote:

Or, even beyond that, go straight to the source and have someone make
a tweaked version of the CADR hardware on a chip:

http://www.unlambda.com/cadr/index.html

Now THERE's a project idea - has anyone ever considered attempting to
implement an ANSI common lisp using the MIT CADR emulator as a
starting point? I suppose if you're down to this level, you might be
able to get to design your own hardware anyway, and if the target is
lisp you might as well make your hardware to support that direction.


1. The issues of bootstrapping are only a very, very, small fraction
of the issues involved in making a good Common Lisp implementation.

2. One of the important basic issues is how to get adequate run-time
performance. Most modern CL implementations need sophisticated
compilers, clever calling conventions and memory coding, and carefully
coded garbage collectors. These are all linked together. The treatment
of multi-threading and interaction with the operating environment cuts
across all of these as well.

3. The CADR system (and its descendants) chose an architecture of a
microcoded uniprocessor, with a specialized tagged memory architecture
to solve the problem of run-time performance. They were competitive at
the time with Lisp compilers on contemporary CPUs, but further
increases in performance depended on hardware improvements to speed up
the microarchitecture, and the resulting software is very hard to port
to general purpose CPUs, as opposed to emulation layers. Once you need
an emulation layer of software, you are basically never going to beat
the Lisp implementations running without that extra layer of overhead,
so this strategy only helps preserve the investment in the original
non-portable software, while continuing to lag in performance.

It is not at all clear that such a machine could be efficiently
implemented with today's available FPGAs, for instance. I'm guessing
that, even if it is possible, such explicitly microcoded CPUs are
probably not the most efficient way to use FPGA gates, and
furthermore, even if you did, the resulting CPU would not compete very
strongly against general purpose CPUs and modern Lisp implementations.
Part of the basis for my belief is that no-one appears to be
successfully creating emulators of old DEC CPUs in FPGA hardware, and
I suppose many more people used those than Lisp Machines; another is
that CPUs designed for FPGAs generally are RISC. I could be quite
wrong.

Even projects to replicate 8-bit microcomputers tend not to give very
exciting results.

.

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