Re: How much tuning does regular lisp compilers do?

On 2008-08-30 18:37:43 +0100, rpw3@xxxxxxxx (Rob Warnock) wrote:

[a very detailed explanation of his Lisp on Atlon cache aligment
experiments]

That's certainly more than what I expected, but then begs the
question of how realistic such improved "cached aligned" loops
might ne in the real world:

Given the byzantine number of bytes per opcode requirement of
the x86 ISA, it is very likely that most loops will need more
than 16 bytes of code between the branch-back and the top of
the loop, thus incurring a systematic "16 bytes fetch cycle"
miss each and every time through the loop.

As for the VM mapping bit, I was just saying that virtual
address 48B68C28 (labbelled FAST in your example) might be
mapped to physical address, say xxxx20, that which the CPU
actually fetches from, and thus your 16 bytes alignment that
holds in VM land might just break after translation.

But thanks for the entertaining explanation :-)
--
JFB

.